module synchronizer #(
    parameter ASIZE=2 // 2^ASIZE == MEMSIZE
)(
    input rclk,
    input rrst,
    input ren,
    input wclk,
    input wrst,
    output yummy
);
    reg [ASIZE:0] cr;
    wire [ASIZE:0] cr_gray;
    reg [ASIZE:0] cw;
    wire [ASIZE:0] cw_gray;
    reg [ASIZE:0] cmw_gray;
    reg [ASIZE:0] crw_gray;
    reg [ASIZE:0] cmr_gray;
    reg [ASIZE:0] cwr_gray;

    always @(posedge rclk) begin
        if(rrst)
            cr<=0;
        else if(ren)
            cr<=cr+1;
    end
    assign cr_gray[ASIZE]=cr[ASIZE];
    assign cr_gray[ASIZE-1:0]=cr ^ (cr>>1);
    always @(posedge rclk) begin
        if(rrst) begin
            cmw_gray<=0;
            crw_gray<=0;
        end else begin
            cmw_gray<=cw_gray;
            crw_gray<=cmw_gray;
        end
    end

    always @(posedge wclk) begin
        if(wrst)
            cw<=0;
        else if(yummy)
            cw<=cw+1; 
    end
    assign cw_gray[ASIZE]=cw[ASIZE];
    assign cw_gray[ASIZE-1:0]=cw ^ (cw>>1);
    always @(posedge wclk) begin
        if(wrst) begin
            cmr_gray<=0;
            cwr_gray<=0;
        end else begin
            cmr_gray<=cr_gray;
            cwr_gray<=cmr_gray;
        end
    end

    assign yummy= cwr_gray != cw_gray;
endmodule

